[#24] New language: Verilog

This commit is contained in:
Radon Rosborough 2020-09-26 19:40:14 -07:00
parent f3af583d1c
commit b9eb65bc00
2 changed files with 18 additions and 0 deletions

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@ -2891,6 +2891,21 @@ BA 64 CR 1/2 TR 1 CH 1 NT C 3+1/5 voff=0
BA 67 CR 7/10 TR 1 CH 16 End of track
`
},
verilog: {
aliases: ["systemverilog", "iverilog", "v"],
name: "Verilog",
main: "main.v",
compile: "iverilog main.v -o main",
run: "./main",
template: `module main;
initial begin
$display("Hello, world!");
end
endmodule
`,
},
vim: {
aliases: ["viml", "vimscript"],

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@ -66,6 +66,9 @@ unlambda
# Vala
valac
# Verilog
iverilog
# Vimscript
vim